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1/24 ? semiconductor MSM5432126/8 description the MSM5432126/8 is a new generation graphics dram organized in a 131,072-word 32-bit configuration. the technology used to fabricate the MSM5432126/8 is oki's cmos silicon gate process technology. the device operates with a single 5 v power supply. features ? 131,072-word 32-bit organization ? single 5 v power supply, 10% tolerance ? refresh: 512 cycles/8 ms ? fast page mode with extended data out (edo) ? write per bit (msm5432128 only) ? byte write, byte read ? ras only refresh ? cas before ras refresh ? hidden refresh ? package: 64-pin 525 mil plastic ssop (ssop64-p-525-0.80-k) (product : MSM5432126-xxgs-k) (product : msm5432128-xxgs-k) xx indicates speed rank. product family ? semiconductor MSM5432126/8 131,072-word 32-bit dynamic ram : fast page mode type with edo preliminary family t rac 50 ns 60 ns operating (max.) 907 mw 880 mw power dissipation cycle time (min.) 110 ns 130 ns MSM5432126/8-50 MSM5432126/8-60 t aa 25 ns 30 ns t cac 15 ns 18 ns standby (max.) access time (max.) 11 mw t oea 15 ns 18 ns 45 ns 935 mw 100 ns MSM5432126/8-45 23 ns 13 ns 13 ns this version: jan. 1998 previous version: dec. 1996 e2l0045-17-y1
2/24 ? semiconductor MSM5432126/8 pin configuration (top view) pin name function a0 - a8 address input power supply (5 v) ground (0 v) nc no connection v cc v ss dq0 - dq31 data input / data output ras row address strobe cas1 - cas4 column address strobe write per bit * / write enable wb * / we oe output enable note: the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. *: msm5432128 only 1 v cc 64-pin plastic ssop v ss 2 dq0 dq31 3 dq1 dq30 4 dq2 dq29 5 dq3 dq28 6 v cc v cc 7 dq4 dq27 8 dq5 dq26 9 dq6 dq25 10 dq7 dq24 11 v ss v ss dq8 dq23 13 dq9 dq22 14 dq10 dq21 15 dq11 dq20 16 v cc v cc 17 dq12 dq19 18 dq13 dq18 19 dq14 dq17 20 dq15 dq16 v ss v ss nc cas1 nc cas2 nc cas3 wb * / we cas4 ras oe nc a8 a0 a7 a1 a6 a2 a5 a3 a4 v cc v ss 12 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
3/24 ? semiconductor MSM5432126/8 block diagram ras cas4 cas3 a0 - a8 wb / we oe dq8 - dq15 dq16 - dq23 v cc v ss dq0 - dq7 dq24 - dq31 cas2 cas1 timing generator refresh control clock column address buffers internal address counter row address buffers row deco- ders word drivers memory cells sense amps column decoders 8 8 99 i/o controller i/o controller 32 i/o selector input buffers output buffers output buffers input buffers 32 8 8 8 8 8 8 8 8 on-chip v bb generator input buffers output buffers output buffers input buffers 8 8 8 8 8 8 8 8 i/o controller i/o controller
4/24 ? semiconductor MSM5432126/8 electrical characteristics absolute maximum ratings recommended operating conditions input high voltage power supply voltage input low voltage v cc v ss v ih v il max. 5.5 0 v cc + 1.0 0.3 v v v v typ. 5.0 0 min. 4.5 0 3.0 C0.3 (ta = 0c to 70c) parameter unit symbol capacitance input capacitance c in c io pf pf input / output capacitance max. 8 9 typ. (v cc = 5 v 10%, ta = 25c, f = 1 mhz) parameter unit symbol rating C0.5 to 7.0 50 1 0 to 70 C55 to 150 v ma w c c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t i os p d t opr t stg parameter unit symbol
5/24 ? semiconductor MSM5432126/8 dc characteristics average power supply current ( cas before ras refresh) ras = cycling, cas before ras 1, 2, 4 ma 130 140 i cc5 average power supply current (fast page mode) ras = v il , cas cycling, t hpc = min. 1, 2, 4 160 165 i cc4 ma input leakage current output high voltage condition note average power supply current (operating) power supply current (standby) output low voltage output leakage current unit average power supply current ( ras only refresh) parameter i oh = C0.1 ma i ol = 0.1 ma 0 v < v in < v cc ; all other pins not under test = 0 v 0 v < v out < 5.5 v output disable ras , cas cycling, t rc = min. ras 3 v cc C 0.2 v, cas 3 v cc C 0.2 v ras = cycling, cas = v ih , t rc = min. v v m a m a 1, 2, 3 ma ma 1, 2, 3 ma max. v cc 0.8 10 10 130 2 130 min. 2.0 0 C10 C10 max. v cc 0.8 10 10 140 2 140 min. 2.0 0 C10 C10 symbol v oh v ol i li i lo i cc1 i cc2 i cc3 MSM5432126/8 -60 MSM5432126/8 -50 (v cc = 5 v 10%, ta = 0c to 70c) 150 170 max. v cc 0.8 10 10 150 2 150 min. 2.0 0 C10 C10 MSM5432126/8 -45 notes: 1. specified values are obtained with minimum cycle time. 2. i cc is dependent on output loading. specified values are obtained with the output open. 3. address can be changed once or less while ras = v il . 4. address can be changed once or less while cas = v ih .
6/24 ? semiconductor MSM5432126/8 ac characteristics (1/2) parameter symbol note unit t rc t prwc t aa t cac t cpa t rasp t cas t rcd max. min. max. min. MSM5432126/8 -60 MSM5432126/8 -50 t hpc t rac t rez t rsh t csh t t t rp t ras t rad t asr t rah t asc t cah t ar t rcs t rch t rrh t wcs t wch t rwc t ral t crp t cp access time from column address column address hold time referenced to ras column address set-up time row address set-up time access time from cas column address hold time cas pulse width cas precharge time (hyper page mode) access time from cas precharge cas to ras precharge time cas hold time output buffer turn-off delay time from ras fast page mode cycle time fast page mode read-modify-write cycle time row address hold time ras pulse width (hyper page mode only) random read or write cycle time ras to cas delay time read command hold time read command set-up time read modify write cycle ras precharge time read command hold time referenced to ras access time from ras ras to column address delay time column address to ras lead time ras pulse width ras hold time transition time (rise and fall) write command set-up time write command hold time ns 130 110 ns 30 25 ns 18 15 ns 35 30 ns 35 3 35 3 ns 100k 60 100k 50 ns 80 70 ns 10k 9 10k 8 9 20 20 ns 24 22 ns 60 50 5 ns 20 3 20 3 ns 64 54 ns 14 14 ns 60 50 ns 10k 60 10k 50 10 15 15 0 0 9 7 0 0 10 8 40 35 0 0 6, 12 0 0 6 0 0 0 0 10 8 4, 10 4, 9 4, 13 4, 9,10 3 ns 42 35 ns 30 25 ns ns ns ns ns ns ns ns ns ns ns 170 145 ns 28 24 8 6 9 8 ns ns 8, 12 t cez output buffer turn-off delay time from cas 5 ns 20 3 20 3 t crl cas "h" to ras "h" lead time 0 0ns t rcl ras "h" to cas "h" lead time 0 0ns t doh data output hold after cas low 11 3 3ns MSM5432126/8 -45 max. 23 13 28 35 100k 10k 45 20 10k 32 22 20 min. 100 3 45 65 7 20 20 3 49 12 45 45 15 0 6 0 7 30 0 0 0 0 7 135 22 6 7 3 0 0 3 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3 13 15 12 12 12 12
7/24 ? semiconductor MSM5432126/8 ac characteristics (2/2) parameter symbol note unit t ds t rwd t cwd t dzc t dzo t csr t ref t wsr max. min. max. min. MSM5432126/8 -60 MSM5432126/8 -50 t dhr t awd t oea t chr t rpc t oez t oeh t roh t rwh t ms t mh t dh column address to we delay time cas hold time for cas before ras cycle cas set-up time for cas before ras cycle cas to we delay time data hold time data hold time referenced to ras data set-up time data to cas delay time data to oe delay time write-per-bit mask data hold time write-per-bit mask data set-up time oe command hold time refresh period ras hold time referenced to oe ras precharge to cas active time ras to we delay time wb hold time access time from oe wb set-up time output buffer turn-off delay time from oe ns 0 0 ns 40 35 ns 0 0 ns 0 0 ns 20 3 20 3 ns 10 8 ns 80 70 ms 8 8 0 0 ns 40 35 ns 50 45 ns 18 15 ns 10 9 ns 10 8 ns 10 10 ns 12 10 8 7 0 0 10 8 8 8 ns ns ns ns ns 10 8 7, 12 7, 12 8 t wcr t wp t rwl t cwl write command to cas lead time write command to ras lead time write command hold time referenced to ras write command pulse width 40 35 10 9 10 9 10 9 ns ns ns ns t wez output buffer turn-off delay time from we 3 3ns 20 20 5 5 t och oe "l" to cas "h" lead time ns 10 10 t cho cas "h" to oe "l" lead time ns 10 10 t oep high-z command pulse width ns 12 10 t oed oe to data-in delay time ns 12 12 16 16 16 16 t cpt cas precharge time (refresh counter test) ns 30 25 MSM5432126/8 -45 max. min. 0 32 0 0 20 3 6 65 8 0 30 42 13 8 6 10 10 6 0 7 7 30 8 8 8 320 10 10 10 12 20 t wpe wb / we pulse width (output disable) ns 12 10 10 14 15 12 13 12 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3
8/24 ? semiconductor MSM5432126/8 notes: 1. an initial pause of 200 m s is required after power-up followed by any 8 ras cycles (example : ras only refresh) before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas before ras cycles instead of 8 ras cycles are required. 2. the ac characteristics assume at t t = 3 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . input levels at the ac testing are 3.0 v/0 v. 4. data outputs are measured with a load of 30 pf. dout reference levels : v oh /v ol = 2.0 v/0.8 v. 5. t rez (max.), t cez (max.), t wez (max.) and t oez (max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. this parameter is sampled and not 100% tested. 6. either t rch or t rrh must be satisfied for a read cycle. 7. these parameters are referenced to cas leading edge of early write cycles and to we leading edge in oe controlled write cycles and read modify write cycles. 8. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and the data out pin will remain open circuit throughout the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read modify write cycle and the data out will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out is indeterminate. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only: if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only: if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11. this is guaranteed by design. (t doh = t cac - output transition time) this parameter is not 100% tested. 12. these parameters are determined by the earliest falling edge of cas1 , cas2 , cas3 , or cas4 . 13. these parameters are determined by the latest rising edge of cas1 , cas2 , cas3 , or cas4 . 14. t cwl should be satisfied by all cas es. 15. t cp and t cpt are determined by the time that all cas es are high. 16. only msm5432128.
9/24 ? semiconductor MSM5432126/8 casn -dq function table cas1 h h cas2 h h cas3 h h cas4 h l dq0-7 * * dq8-15 * * dq16-23 * * dq24-31 * enable h h l h * * enable * h h l l * * enable enable h l h h * enable * * h l h l * enable * enable h l l h * enable enable * h l l l * enable enable enable l h h h enable * * * l h h l enable * * enable l h l h enable * enable * l h l l enable * enable enable l l h h enable enable * * l l h l enable enable * enable l l l h enable enable enable * llll enable enable enable enable read cycle write cycle enable valid data-out write data * high-z don't care write cycle function table a b ras falling edge code cas or wb / we falling edge function c wb / we dq dq l write mask write data h ( * 2) don't care write data rwm ( * 1) write per bit rw normal write write mask : 'l' = mask, 'h' = no mask (*1): msm5432128 only. (*2): in case of MSM5432126, don't care.
10/24 ? semiconductor MSM5432126/8 timing waveform read cycle (outputs controlled by ras ) ras address wb / we dq0 - dq31 cas1 | cas4 "h" or "l" oe t rc t ras t rp t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t roh t oea t cac t aa t oez t rez open valid data-out t crl t ar t rac
11/24 ? semiconductor MSM5432126/8 read cycle (outputs controlled by cas ) ras address wb / we dq0 - dq31 cas1 | cas4 "h" or "l" oe t rc t ras t rp t ar t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t oez t cez open valid data-out t rcl t rac
12/24 ? semiconductor MSM5432126/8 write cycle (early write) ras cas1 | cas4 address t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" wb / we a t rwh t wp t wsr dq0 - dq31 bc t mh t ds t dh t ms oe t rwl t cwl t dhr t wch t wcr t wcs
13/24 ? semiconductor MSM5432126/8 write cycle ( oe control write) ras cas1 | cas4 address t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" wb / we a t rwh t wsr dq0 - dq31 bc t mh t ds t dh t ms oe t rwl t cwl t dhr t wcr t wp t oeh t oed t rcs
14/24 ? semiconductor MSM5432126/8 read modify write cycle ras cas1 | cas4 address t rwc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" wb / we a t rwh t wsr dq0 - dq31 bc t aa t ds t dh t ms oe t rwl t cwl t rwd t wp t oeh t awd t oea t rac t cac t mh t oed t oez t rcs out t dzc t dzo t cwd
15/24 ? semiconductor MSM5432126/8 fast page mode read cycle with edo ras address wb / we dq0 - dq31 cas1 | cas4 oe row column t crp t rp t rasp t cas "h" or "l" column column t rcd t cp t cas t cas t hpc t cah t asc t rad t rcs t rrh t ar t aa valid data-out t rah t asr t cah t asc t cah t asc t rc t csh t crp t cp t rsh t ral t rch t rcs t rch t rcs t rch t cac open t rac valid data-out valid data-out t oea t cac t cac t rez t doh t doh t oez t aa t aa t cpa t cpa
16/24 ? semiconductor MSM5432126/8 fast page mode write cycle (early write) ras address wb / we dq0 - dq31 cas1 | cas4 oe "h" or "l" t asr row column column column a b t rah t asc t rad t cah t asc t cah t cah t asc t crp t rcd t cas t ar t rp t rasp t rc t csh t hpc t rsh t crp t cas t cas t cp t ral t wsr t rwh t cwl t wcs t wp t wch t cwl t wcs t wp t wch t cwl t wcs t wp t wch t rwl t wcr t ms t mh c t ds t dh c t ds t dh c t ds t dh t cp t dhr
17/24 ? semiconductor MSM5432126/8 fast page mode read modify write cycle ras address wb / we dq0 - dq31 cas1 | cas4 oe "h" or "l" t asr row column column column a b t rah t asc t rad t cah t asc t cah t cah t asc t crp t rcd t cas t ar t rp t rasp t rc t csh t prwc t rsh t crp t cas t cas t cp t ral t wsr t rwh t cwd t rcs t cwd t rwd t ms t mh t cp t awd t wp t cwl t awd t cwl t wp t cwd t rwl t cwl t wp t oea t oea t awd t oea t oeh t aa t oez t oed out t rac t cac t dh t ds t aa t oez t oed out t dh t ds t cac out t cac t aa t ds t dh t oez t oed cc c t roh
18/24 ? semiconductor MSM5432126/8 ras only refresh cycle ras address cas1 | cas4 t crp t rp t ras t rpc row t asr t rah t rc "h" or "l" note: dqs are open, wb / we , oe = "h" or "l"
19/24 ? semiconductor MSM5432126/8 cas before ras refresh cycle ras casn t rp t ras open t rc t rpc t cp t csr t chr t cez t rp dq0 - dq31 note: wb / we , oe , a0 - a8 = "h" or "l"
20/24 ? semiconductor MSM5432126/8 hidden refresh read cycle ras cas1 | cas4 address oe "h" or "l" wb / we dq0 - dq31 t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t rah t asc t cah row column t rcs t ral t rrh t aa t roh t oea t cac t rac t oez valid data-out t rez
21/24 ? semiconductor MSM5432126/8 hidden refresh write cycle ras address wb / we dq0 - dq31 cas1 | cas4 oe "h" or "l" t asr row column t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral t rwl t chr t ras t rc t rp t ar t wp t wch t wcr t wcs t wsr t rwh c a t dhr t ms t mh t dh t ds b
22/24 ? semiconductor MSM5432126/8 ras address wb / we dq0 - dq31 cas1 | cas4 oe t ras t asc t cpt t rsh t cah t cas "h" or "l" t wp t cwl t rp valid data-out open t aa t cez t cac open t rcs t rwl valid data-out t rcs t awd t cwd t rwl t wp t cwl t cac t oez t chr t csr column t rch t rrh t oez t oea t roh t wch t wcs t dh valid data-in t ds t dh t oed t oea t ds valid data-in read cycle write cycle wb / we oe dq0 - dq31 read modify write cycle wb / we oe dq0 - dq31 open t aa t aa t ral cas before ras refresh counter test cycle
23/24 ? semiconductor MSM5432126/8 "h" or "l" t ar ras cas1 | cas4 address row column column column t rasp t rc t rp t crp t rcd t csh t cas t hpc t cp t cas t cp t cas t cp t cas t rsh t crp t asr t rah t asc t rad t cah t asc t cah t asc t cah column t asc t cah t ral wb / we t rcs t rrh t rch t rch t wpe oe t oea t rac t cac t aa t cho t oep t och t oep dq0 - dq31 t aa t cac t doh t cpa valid data-out valid data-out t oez t oea valid* data-out t aa t cac t oez valid* data-out t wez t oea t aa t cac valid data-out t rez * : same data open t rcs fast page mode read with edo high-z operation
24/24 ? semiconductor MSM5432126/8 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop64-p-525-0.80-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.34 typ. mirror finish

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